Chap 5. Memory

Chap 5. Memory

* Memory Hierarchy ( register - cpu cache - Dram - second Storage -archival Storage )

* Cache (hit / miss / hit rate)

* Cache principle - locality ( temporal, spatial ) 

* Cache access/ saving -> Tag/ Index/ offset (Tag + Memory 's last addr, valid)

* offset -> word size(block size) , index 

* block size, miss rate /  block size quadratic equation (too many - cache volume , too few - around data)

* block size 4 times -> miss rate half

* cache time - set up time(first data coming) + transfer time (around data)

* hiding transfer time performance up ( early restart, critical word first)

* cache process (pc-4, data, field , reply)

* write thru / write back

* write thru( register diameter - word / cache diameter - 4 word, etc.. ) / write back ( multi cpu can't )

* cache cpu time - Clock cycle time * ( cpu cycle + memory stall cycle )

Memory stall cycle = (memory access instruction / total instruction) * miss rate * miss penalty 

* Associative cache ( n- way Full associative cache, 1 - way Direct mapped cache ) 

* pros and cons ( miss rate down // hit time up, HW cost )

* Cache level ( low level -> rapid, small )

* Cache performance compute ( ns -> cycle * miss rate )